1. Field of the Invention
The present invention relates in general to determining signal quality in a digital system and, more particularly, to determining signal quality of clocked signals applied to a chip receiver.
2. Description of the Related Art
In processing systems (e.g., computers, handheld devices, etc.) the signal quality of synchronous signals must be in compliance with the specifications of the device. Such signals are commonly found in busses where the signals must arrive at their final destination point together and are sampled by a common clock. If the signal quality is not in compliance with the device specifications, the device will typically signal a parity error or other error type, and this typically causes a system reboot or requires the retransmission of data.
Measurement of high speed signals in the prior art utilize a voltage reference to determine when the receiver sees a high or low reference. Chip vendors will typically specify a minimum setup time and minimum hold time at which the vendor will guarantee that the device will operate properly. Oscilloscope images are visually compared to specifications to determine if there is sufficient set-up and hold time at the specified voltage levels.
It is typical to test the signal quality of a system before the system is made available to a consumer, and/or during system start-up when the system is actually in use. The set-up, hold, rise, and fall times of the signals are usually measured with an oscilloscope referenced to the receiving clock and the signal pad of the component being tested. This measuring process can take days or weeks to accomplish, especially when some chips have greater than 1,000 signals which must be measured.